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Package tyes:SOP/ZIP/TO;
Material:Die/wafer;
Kerf Width≥60μm;
Chip size:0.45*0.45~10*10mm(thickness≥0.15mm);
Minimum pad size 50μm;
Minimum pad pitch 55μm;
minimum pad thickness 0.8μm;
Chip attachment method:solder/conductive adhesive/insulating adhesive/DAF;
Maximum overflow distance0.25mm;
Bonding with 20~50μm copper wire or gold wire/with 20~200 Aluminum wire;
Wire loop height≥0.1mm;
Supprt chip stacking packaging;
Support multi-chip packaging.
